The present invention relates generally to integrated circuit (IC) designs, and more particularly to sense amplifiers operated under Hamming distance methodology for improving performance or reducing layout areas thereof.
A differential amplifier is a circuit module that generates outputs in response to a voltage difference between various inputs. It is commonly used in IC chips, such as memory devices, for amplifying sensed data signals. The differential amplifier is typically consisted of electronic components that can be grouped into symmetric halves, each being connected to a differential input. The electronic components of the two symmetric halves need to match in their dimensions, materials and structures in order to ensure that the outputs from the differential amplifier accurately reflects the voltage difference between the inputs. As a result, the size of the differential amplifier cannot be scaled down easily because the smaller the amplifier the more susceptible it is to mismatch due to manufacturing process variations.
FIG. 1 illustrates a first distribution curve 102 of a first group of differential sense amplifiers and a second distribution curve 104 of a second group of differential sense amplifiers, which are half the size of the differential sense amplifiers in the first group. The offset voltages for each group of differential sense amplifiers are normally distributed, in which the curve 102 is more concentrated and the curve 104 is more spread out. The curves 102 and 104 show that there are more small amplifiers outside a predetermined range of input swing than the large ones. This raises reliability issues as the differential sense amplifiers are scaled down.
FIG. 2 illustrates a conventional differential sense amplifier within a layout area 202. A new design for differential sense amplifiers has been proposed to reduce the layout area without compromising their reliability. Naveen Verma, Anantha P. Chandrakasan, “A 65 nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 64-65, February 2007. As shown in FIG. 3, the layout area 202 is split into two halves 302 and 304, each of which is implemented with a differential sense amplifier. Assume that the offset voltages for the large amplifier in the layout area 202 and the amplifier in the layout area 302 or 304 are normally distributed, and the probability of failure for the small amplifier is 0.001, which is translated into a z value of 3.09 in a standard normal distribution. The probability of failure for the large differential sense amplifier is therefore 0.000006, which is obtained by looking up the standard normal distribution table with a z value of 4.369, i.e., 3.09*(2)1/2 as the large amplifier is twice bigger than the small amplifier. Although the probability of failure for one small amplifier (0.001) is higher than that for one large amplifier (0.000006), the probability of two small amplifiers failing at the same time (0.000001=0.001*0.001) is lower than the probability of failure for one large amplifier. In other words, for the same reliability level, the overall size of two small amplifiers 302 and 304 would be smaller than one large amplifier 202.
The conventional dual sense amplifier design requires an initial testing process where all the sense amplifiers are scanned in order to select the sense amplifier with better performance from each pair of sense amplifiers. Additional registers are required for storing the status of the sense amplifiers in support of their operation. As a result, the conventional dual sense amplifier design can be quite complicated and resource-consuming.
Thus, what is needed is a simple design for differential sense amplifiers that reduces the layout areas without compromising the reliability.